Difference between assume and assert statement?

SystemVerilog
1

I do understand assert(property_name) will check for failurs in property or sequence and
Cover(property_name) will check for coverage in property or sequence. What is the actual use of assume statement?

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2

The distinction is mainly for formal tools. An assume directive is the same as an assert in simulation. A formal tool uses an assume directive as a constraint depending on what level in the hierarchy it is placed.

3

Hi Dave,
thansks for ur reply. Can u please elaborate on the same?

Rakesh

4

In reply to rakeeee:

From SystemVerilog Assertions Handbook, 3rd Edition

See http://systemverilog.us/assert_assume_restrict.pdf

5

As a methodology note, we suggest you use “assume” if you are writing a property solely based on design inputs. If it is on outputs/internal signals/mix, then use assert.

And yes, we delve into details on this in our SVA book (www.systemverilog.us)

Regards
Ajeetha, CVC

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