Diff between $rose and $posedge in system verilog

SystemVerilog
1

what is difference between $rose and $posedge in system verilog.
or explain with example like $rose(a) and $posedge(a) then what is it’s waveform…!

1 Like
2

In reply to Sunny hirpara:
At a high level there is no difference between $rose and $posedge. $rose returns true or false while $posedge returns an event. $rose can be used in expressions but not $posedge

3

In reply to Sunny hirpara:
Hi,

  1. $rose gives out an sampled boolean value by checking whether the signal had risen from previous edge(whatever is given) to the current edge. When you say $rose(a), it gives 1 or 0. Moreover $rose is set to one if the least significant bit of a changes from any value(0,x,z) to 1 else it is set to 0.
  2. @posedge is an event.It is checked instantly.It does not return any value.

You mean to say @(posedge) right? not $posedge.

4

In reply to Sunny hirpara:

There is no such thing as $posdege(a). There is @(posedge a). This is an event control that blocks a process waiting for an update to ‘a’ where the LSB goes from zero to non-zero.

$rose(a) is a sampled function that must be used in the context of some other synchronous event. It returns true if the LSB of ‘a’ was zero in the previous cycle and is now 1 ub the current cycle. Otherwise it returns false.

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Thank you Dave,Anudeep,arunj…!