Diff between $rose and $posedge in system verilog

SystemVerilog
3

In reply to Sunny hirpara:
Hi,

  1. $rose gives out an sampled boolean value by checking whether the signal had risen from previous edge(whatever is given) to the current edge. When you say $rose(a), it gives 1 or 0. Moreover $rose is set to one if the least significant bit of a changes from any value(0,x,z) to 1 else it is set to 0.
  2. @posedge is an event.It is checked instantly.It does not return any value.

You mean to say @(posedge) right? not $posedge.