Decremental for loop is not executing in systemverilog

SystemVerilog
,
1

Hi,

While i am trying to run decrement loop in any method or in initial begin … end, It is not getting executed(It’s not showing any error). Don’t know the reason. The following code describes the same.

module top;
  class decr_check;
    task xyz;
      for(int j=5; j<0; j--) $display("j = %0d",j);
    endtask
  endclass
  decr_check h_obj;
  initial begin
    h_obj = new();
    h_obj.xyz(); 
  end
endmodule

Output :
S i m u l a t i o n R e p o r t
Time: 0 ns

Kindly help me to understand the concept.

2

In reply to Jaymin_Vaghela:

You have an error in your for loop for(int j=5; j<0; j–) $display(“j = %0d”,j); i <0 this will never be met since i starts at the value of 5, I guess you need to change to the following(depending on what you want)


for(int j=5; j>0; j--) $display("j = %0d",j);

HTH,

-R

3

In reply to rgarcia07:

Ohh yes you are right. It’s a typo. Thanks rgarcia07.