Decremental for loop is not executing in systemverilog

SystemVerilog
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2

In reply to Jaymin_Vaghela:

You have an error in your for loop for(int j=5; j<0; j–) $display(“j = %0d”,j); i <0 this will never be met since i starts at the value of 5, I guess you need to change to the following(depending on what you want)


for(int j=5; j>0; j--) $display("j = %0d",j);

HTH,

-R