Declaring an object and instantiating it in the run_phse

UVM
1

Hi,
I am quite new to UVM but I took the courses in this site and I thought I understood them. But all confidence is gone when I got the issue below. Although I fixed it, I didn’t understand what was the problem and why it got fixed.

The code below build successfully but I don’t understand why it doesn’t if I move the instantiation of ts_req_transaction outside the forever loop right below the declaration. Any ideas why I get syntax error?

virtual task run_phase(uvm_phase phase);
      
      rgx_usc2_generic_store_req_transaction#(.ADDR_BITS(TS_ADDRESS_WIDTH),.MASK_BITS(TS_MASK_WIDTH),.DATA_BITS(TS_DATA_WIDTH)) ts_req_transaction;
      //
      // ref model state
          
      ref_model_state_type ref_model_state;
      ref_model_state  = READ_COEF_FROM_TS;
      
      forever begin : run_loop
         case (ref_model_state)
           //other cases
           READ_COEF_FROM_TS :
             begin
                //READ COEF from TS
                ts_req_transaction  = rgx_usc2_generic_store_req_transaction#(.ADDR_BITS(TS_ADDRESS_WIDTH),.MASK_BITS(TS_MASK_WIDTH),.DATA_BITS(TS_DATA_WIDTH))::type_id::create("ts_req_transaction", this);
                // doing some stuff
             end
           default : 
             begin
                `uvm_fatal("Run phase", "Simulation stopped when reached an undefined state");
             end
         endcase
      end : run_loop
      
   endtask: run_phase
2

In reply to obd_00:
It would help to show the code you have trouble with and the syntax error you are getting.

By instantiation, do you mean the line that call for the construction of an object (create()?

Verilog and SystemVerilog require that all identifiers be declared before they can be referenced. This requirement comes in to play when trying to resolve hierarchical references.

3

In reply to dave_59:

Thanks for the reply and yes that is what I meant by instantiation. The code with trouble is below. Moving the create statement below the declarations and then declare another identifier. Verdi is not saying anything useful, just syntax error at the line of “ref_model_state_type ref_model_state;”

virtual task run_phase(uvm_phase phase);
 
      rgx_usc2_generic_store_req_transaction#(.ADDR_BITS(TS_ADDRESS_WIDTH),.MASK_BITS(TS_MASK_WIDTH),.DATA_BITS(TS_DATA_WIDTH)) ts_req_transaction;
                ts_req_transaction  = rgx_usc2_generic_store_req_transaction#(.ADDR_BITS(TS_ADDRESS_WIDTH),.MASK_BITS(TS_MASK_WIDTH),.DATA_BITS(TS_DATA_WIDTH))::type_id::create("ts_req_transaction", this);
      //
      // ref model state
 
      ref_model_state_type ref_model_state;
      ref_model_state  = READ_COEF_FROM_TS;
 
      forever begin : run_loop
         case (ref_model_state)
           //other cases
           READ_COEF_FROM_TS :
             begin
                //READ COEF from TS

                // doing some stuff
             end
           default : 
             begin
                `uvm_fatal("Run phase", "Simulation stopped when reached an undefined state");
             end
         endcase
      end : run_loop
 
   endtask: run_phase