why two state data types are introduced in SystemVerilog? Why are they are specially meant to be for simulation?
In reply to Ram130625@:
The two-state data types, bit and logic, were introduced in SystemVerilog to provide a more efficient way of representing digital signals in simulation.
Two-state data types, on the other hand, only have two possible values (0 or 1), which makes simulation faster and more efficient.
Additionally, two-state data types are more consistent with the behavior of digital hardware, which only has two possible states. This makes it easier to write and understand Verilog code that accurately models hardware behavior.
Overall, the introduction of two-state data types in System Verilog has been a significant improvement for simulation performance and accuracy.
In reply to chetansahu:
That is only part of the story. Real hardware is made from combination analog current and voltage values. Digital or integral types are level abstraction used in RTL for both simulation and synthesis. Verilog wires use a simplified state/strength system that accommodate tri-state bus modeling, switch-level modeling. Verilog variables further simplifies that down to 4-states: 0, 1, X representing an ambiguous state, and Z representing no strength(HiZ)
RTL synthesis tools only consider the 2-states types 0 and 1 for evaluating boolean expressions. It can use the X state in a numeric literals for don’t care optimization. But no signal can propagate X state through any signal. So you can think of 4-state data types purely for simulation. X states are used to represent uninitialized logic or error conditions inside the DUT. The testbench is a different story. It’s more like software and there is no need for the overhead of representing the 2 extra states.