In reply to Ram130625@:
The two-state data types, bit and logic, were introduced in SystemVerilog to provide a more efficient way of representing digital signals in simulation.
Two-state data types, on the other hand, only have two possible values (0 or 1), which makes simulation faster and more efficient.
Additionally, two-state data types are more consistent with the behavior of digital hardware, which only has two possible states. This makes it easier to write and understand Verilog code that accurately models hardware behavior.
Overall, the introduction of two-state data types in System Verilog has been a significant improvement for simulation performance and accuracy.