Although the 2017 SystemVerilog LRM section 11.8.1 states that concatenate results are unsigned it doesn’t mention anything about its data type. Is it by default set to logic?
In reply to vasilissoti:
The result is a packed array of logic with a width the sum of widths of its operands. Similar to your question on numeric literals, it has to be logic in case any of its operands are 4-state.