module test (dff_if.tb intf);
initial begin
fork
drv();
mon();
join
$finish
end
task drv();
repeat(10) begin
@(intf.cb);
intf.d<=$random();
$display("d=%0d q=%0d",intf.q,intf.d);
end
endtask
task mon();
logic q;
@(intf.cb);
$display("q=%0d",intf.q);
endtask
endmodule
interface dff_if (input clk);
logic d;
logic q;
clocking cb @(posedge clk);
default input #1ns output #1ns ;
input q;
output d;
endclocking
modport dut (input d,input clk,output q );
modport tb (clocking cb);
endinterface
module top();
bit clk;
always #2 clk=~clk;
dff_if dut_if(clk);
dff dut (dut_if);
test tb_inst (dut_if);
endmodule
///dut
module dff (dff_if.dut intf);
always @(intf.clk)
begin
intf.q <= intf.d;
end
endmodule
In reply to rakesh varikela:
Please use code tags making your code easier to read. I have added them for you.
What is your question? Does the code work? Are there errors? Does it function as you expect?
Posting code and stating “can u check the errors in code” isn’t going to make anyone want to help if you can’t articulate your issue.