In reply to ben@SystemVerilog.us:
The assertion with the task could have been written as
property p_dfromclk;
realtime t;
@(sig1) (1, t=$realtime) ##1
@(posedge clk) $realtime -t <= 21ns &&
$realtime -t >= 20ns;
endproperty
ap_dfromclk: assert property(p_dfromclk) ok3=ok3+1;
else err3=err3+1;
The reason I initially wrote it with the task is because that’s how I saw it: at the leading clocking event (the @(sig1) I fire an automatic task that has a life of its own. This is explained in my paper "Understanding the SVA Engine Using the Fork-Join Model
Verification Horizons - July 2020 | Verification Academy
Using a model, the paper addresses important concepts about attempts and threads. Emphasizes the total independence of attempts.
You should read this paper if you want to relly understand a good modeling of assertions.
The updated model with this new property is at (4) - EDA Playground
The simulation results are at