In UVM, I want to create two objects as below in a build_phase. Both have same name argument but parent argument is different. What will happen? Is it allowed to do?
obj_a = CLASS_A::type_id::create(name,this);
obj_b = CLASS_B::type_id::create(name,handle_c.obj_d);
In reply to DhavalP:
It is allowed, but very unusual. When creating any hierarchy, siblings cannot have the same name. This is just like files and directory names.
The UVM has no way of knowing if the class variable holding the handle to the component has the same identifier name as the strings passed to the constructor. It also has no way of knowing if the class variables have the same hierarchy as the hierarchy passed to constructor. For debugging, it is best to keep them the same.
In reply to dave_59:
It appears that the obj_b has the same leaf level name as obj_a, but they are placed in a different hierarchy. In that sense, they are not really siblings. So in my opinion, this should be perfectly legal, but may not adhere strictly to paradigms of object oriented design.
In reply to dave_59:
Hi Dave,
I think you are talking about different string name argument in constructor new and while creating component using create.
I am talking about providing different parent argument(second argument in create method call) in two different components while string name argument(first argument in create method call) is same for both objects.
obj_a = CLASS_A::type_id::create(“obj_a”,this);
obj_b = CLASS_B::type_id::create(“obj_a”,handle_c.obj_d);
In reply to logie:
I think was are saying the same thing. But I’ll add that SystemVerilog has no built-in concept of owner relationships. A class object has no knowledge of which object created it unless the user defines a database structure that contains that information, which is what uvm_component does.
In reply to dave_59:
I know what you are trying to do, and it can be done. You can have same leaf names in different levels of the hierarchy, but very irregular.