In reply to feiphung:
OK, since the $past is within the always @(posedge clk) it gets it clocking event from that. I tried the follwing code (complete model below) and I got the same coverage for ac00, ac0, and ac. BTW, Adding labels to your cover statement makes debugging a bit easier.
always @(posedge clk) begin
if(a) ac00: cover($past(b));
if(a) ac0: cover($past(b, 1, 1, @(posedge clk)));
if(a) ac: cover property ($past(b, 1, 1, @(posedge clk)));
end
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
always @(posedge clk) begin
if(a) ac00: cover($past(b));
if(a) ac0: cover($past(b, 1, 1, @(posedge clk)));
if(a) ac: cover property ($past(b, 1, 1, @(posedge clk)));
end
initial begin
bit va, vb;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb) with
{ va dist {1'b1:=1, 1'b0:=3};
vb dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
end
$stop;
end
endmodule
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