In reply to ben@SystemVerilog.us:
Look carefully at code surrounding cover($past(full)).
It has clocking sampling event.
always_ff @(posedge write_clk)
if (first_write_clock_had_passed)
cover($past(full)&&($past(write_en))&&(full));
Note: I have split cover($past(full)&&($past(write_en))&&(full)); into three separate cover() and this is how I debug why the larger cover() statement failed.
Now the question is why cover($past(full)) failed but cover(full) passed ?