Controlling clock generation

SystemVerilog
,
1

i need to generate a clock that can be controlled by a signal driven by driver.
my scenerio is like >> whenever CS will go low the clock start toggling.

i have implented a clock generation inside interface like…
interface my_interface;
bit clk;
bit start_clk;

always
begin
if(start_clk)
#5 clk =~clk;
end
endinterface

inside driver run phase i have assinged the value of start_clk like vif.start_clk=1’b1;
but its not working.

2

In reply to Abhisek Sarkar:

Hi Abhisek,

You should try something like as follows:

interface my_interface;
bit clk;
bit start_clk;

always@(start_clk)
begin
while(start_clk)
begin
if(!start_clk)
break;
#5 clk =~clk;
end
end
endinterface

It will work!

3

In reply to Abhisek Sarkar:


interface my_interface;
  bit clk;
  bit clk_enable;
  wire clk_out;
  
  initial begin
    clk = 1'b0;
    clk_enable = 1'b1;
    forever #5 clk = ~clk;
  end

  assign clk_out = clk & clk_enable;

  function clk_control(input bit ctrl);
    clk_enable = ctrl;
  endfunction

endinterface