Controlling clock generation

In reply to Abhisek Sarkar:

Hi Abhisek,

You should try something like as follows:

interface my_interface;
bit clk;
bit start_clk;

always@(start_clk)
begin
while(start_clk)
begin
if(!start_clk)
break;
#5 clk =~clk;
end
end
endinterface

It will work!