Constraint

SystemVerilog
,
1

Hi,
How to write a constraint in system verilog to generate random elements in an array in descending order?

Regards,
Sravan

2

Hi Sravan,
One of the methods to implement this would be to generate the random elements within a range and in the post randomise sort it descending.

3

Th following x_val constraint should be abl to generate in descending order.


class AC;
     rand int unsigned x[];
     constraint x_size{x.size == 10;}
     constraint x_val{foreach (x[i])
	                  if(i != x.size-1)
			          x[i]>x[i+1];}
												
     constraint x_v1{foreach (x[i])
			x[i] inside {[1:100]};}

endclass