Constraint sum overflow

SystemVerilog
3

In reply to Desam:

You can simply make the addition include the overflow bit instead of having it truncated.

module abc;
  class a;
    rand int unsigned aa;
    rand int unsigned bb;

    constraint c2 {
      33'(aa + bb) <= 10;
    }
  endclass
 
  a a1 = new();
  initial begin
    a1.randomize();
    $display(a1.aa,,a1.bb);
  end 
endmodule

Also see my DVCon2020 presentation on Verilog expression in SystemVerilog constraints.