In the below example if the “addr” is declared as bit[8:0] the randomization is giving incorrect results. However, if “addr” is declared as bit[31:0] correct output is coming. Can somebody please help me to understand why is this happening? // Incorrect output code class abc; rand bit[8:0] addr[…

No it will not. Run with this code abc h = new; initial begin h.randomize; $displayh(h.addr.sum() with (int'(item))); end

Verification Academy

Sum() in constraint

SystemVerilog

dave_59 July 2, 2025, 9:58pm 2

Constraint sum overflow SystemVerilog

In reply to Desam: You can simply make the addition include the overflow bit instead of having it truncated. module abc; class a; rand int unsigned aa; rand int unsigned bb; constraint c2 { 33'(aa + bb) <= 10; } endclass a a1 = new(); initial begin a1.randomize(); $display(a1.aa,,a1.bb); end endmodule Also see my DVCon2020 presentation on Verilog expression in SystemVerilog constraints.

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