CONSTRAINT ON AN ARRAY WITH SET BITS

SystemVerilog
, , ,
5

In reply to prashantk:

make sure your requirement clear. if you want to put in a class, rand or not rand doesn’t matter.


class my_item;
  rand bit [15:0] available;
  rand bit [3:0]  choose;
  constraint a {
    available != 0;
    available | (1 << choose) == available;
  }
endclass
bit [15:0] AVAILABLE = 'hFF; // given value
my_item item = new();
item.randomize() with (available == AVAILABLE);

if you give me fixed available, and only want to have valid choose, this is good enough.


  bit [15:0] available;
  bit [3:0]  choose;
  std::randomize(available) with {available != 0;}; // given some value
  std::randomize(choose) with {(available | (1<<choose)) == available;}; // inline randomize