CONSTRAINT ON AN ARRAY WITH SET BITS

SystemVerilog
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4

In reply to prashantk:

It helps to show the declarations of the variables you describe. Also, what happens when AVAILABLE == 0?

class bit [15:0] available;
  rand bit [3:0]  choose;
  bit [3:0] list[$];
  function pre_randomize();
     list = {};
     foreach (available[v]) if (available[v]) list.push_back(v);
  endfunction
  constraint c { choose inside {list};}
endclass