Constraint for two consecutive numbers be same

SystemVerilog
1

Hi all,

How to write a constraint for two consecutive numbers are same.

Example pattern: array[15] ----> {3,3,7,5,5,9,6,6,1,4,4,–}

I tried below code but its not working

module conditional_con;
  class frame_t;
    rand int length[10];
    int k;
  
    constraint frame_sizes {
      
      foreach (length[i]){
        if(i!=0)
          i==i+2;
        else
          i==i;
        foreach(length[j]){
          if(j==i || j==i+1){
            if(j!=0)
            length[j]==length[j-1];
            else
              length[j]==length[j];}
          else{
            length[j]!=length[j-1];}}
           
          } 
            
    }
            
            
    
  endclass

  initial begin
     frame_t frame = new();
     integer i,j;
     for (j=0;j < 4; j++) begin
       $write("-------------------------------\n");
       $write("Randomize Value\n");
       i = frame.randomize();
        
       $display("length   : %p",frame.length);
     end
     $write("-------------------------------\n");
  end

endmodule

Thanks,

2

In reply to bsivakumar:

Please use code tags making your code easier to read. I have added them for you.

The requirements for your constraint is not very clear. Looking at your example, it appears you want the first elements to repeat, followed by a non repeating element. Then that pattern repeats. If that is the case, then the size of the array must be a multiple of 3.

module conditional_con;
  class frame_t;
    rand bit [3:0] length[12];
    constraint frame_sizes {
      foreach (length[i])
        i%3==0->{
          length[i] == length[i+1];
          length[i+1] != length[i+2];
        }
    }
  endclass
  frame_t frame = new();
  initial begin
    repeat(4) begin
      $write("-------------------------------\n");
      $write("Randomize Value\n");
      assert(frame.randomize());
      $display("length   : %0p",frame.length);
    end
    $write("-------------------------------\n");
  end
endmodule