Constraint For Specific Value!

SystemVerilog
, ,
2

In reply to MarshallX:
Please use code tags making your code easier to read. I have added them for you.

You have not connected through any constraint of reg_address to any value in reg_address_array.

The dist construct is not a hard constraint that a value in the set of ranges appear, only that values not in the ranges do not appear.

Maybe this helps

class base_b1;
    rand bit [31:0] reg_address_array[$];
 
   constraint b1_c {
      foreach (reg_address_array[i])
         reg_address_array[i] dist {5:/25, 10:/25, [25:50]:/50};
      reg_address_array.or() with (item==25); // 25 must appear at least once
      reg_address_array.or() with (item==50); // 50 must appear at least once
   }
   constraint size_c2 { 
      reg_address_array.size inside {[9:10]};
   }
endclass: base_b1