Constraint for 32 bit addr to be different than prev addr by 2 bits

SystemVerilog
,
5

In reply to n347:


// This code will be helpful for you
class A;
	rand bit [31:0]a;
	// static bit [31:0]a_temp;
	static bit [31:0]aQ[$:10];

	constraint a_a {$countones(a^const'(a))==2;}
	// constraint a_a {$countones(a^a_temp)==2;}

	constraint a_non_rep{unique{a,aQ};}

	function void post_randomize();
		// a_temp=a;
		aQ.push_back(a);
	endfunction
endclass
module top;
	A b=new;
	initial begin
		for(int i=0;i<10;i++)begin
			// b=new();
			b.randomize();
			$display("value of a=%b",b.a);
		end
	end
endmodule