Constraint for 32 bit addr to be different than prev addr by 2 bits

SystemVerilog
,
4

Since most simulators support the $countones system function in constraints, you can do:

class a;
  rand bit [31:0] addr;
  bit [31:0] prev_addr;
  
  function void pre_randomize;
    prev_addr = addr;
  endfunction
  
  constraint addr_constraint {$countones(addr ^ prev_addr) == 2;}
  
endclass : a