Constraining an Object's Object's Variable

SystemVerilog
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2

In reply to dsherman0623:

That should be


logic[15:0] myLogic1;
if(!randomize(myLogic1))  `uvm_error(.. 
.. 
constraint A::myLogic1_const{
  myB.myLogic1[15:14] != 2'b01;} 

 [/systemverilog ] 
Did your code really passed the compiler? 
Ben systemverilog.us