Constrain a relation between arrays of signed values in systemverilog

SystemVerilog
, ,
1

hi SV gurus!

i have a problem constraining a relation (sum of absolute difference) in between values of 2 arrays of signed bits.

here is the example code:



class myclass extends uvm_seq_item;

   rand bit signed [19:0] arr1[16];
   rand bit signed [19:0] arr2[16];

   constraint abs_diff_c {
      foreach(arr1[i]){
         foreach(arr1[j]){
             (arr1[i] + arr2[i] - arr1[j] - arr2[j]) inside [-4095:4095];
         }
      }
   }
   `uvm_object_utils(hel_vis_rs_ms_trans);
endclass

in above example i have 2 arrays each containing 16 signed 20 bit values. the relation between these 2 arrays that i want to constrain is the sum of absolute difference and that should be less than 4096.

the way i do it (or i’m trying to) is to blindly say that the solver should pick values only if sum of differences for all indices fall inside [-4095:4095]. is there any way to achieve this?

2

In reply to banalui:

You can do this adding a helper array so you can use a sum reduction method on it.

class myclass extends uvm_seq_item;
 
   rand bit signed [19:0] arr1[16];
   rand bit signed [19:0] arr2[16];
   rand int differences[16*16];
   constraint abs_diff_c {
      foreach(arr1[i]){
         foreach(arr1[j]){
             (arr1[i] + arr2[i] - arr1[j] - arr2[j]) == differences[i*16+j];
         }
      }
      differences.sum() inside {[-4095:4095]};
   }
   `uvm_object_utils(hel_vis_rs_ms_trans);
endclass