Properly Constraining Signed Logic Dynamic Array

SystemVerilog
3

Would a simple solution be something similar to this:

class my_seq_item extends uvm_sequence_item;
  `uvm_object_utils(my_seq_item)

  rand bit signed [17:0] rx_data[];

  constraint rx_data_c {
    foreach (rx_data[i]) {
      rx_data[i][17:0] inside {[-0.7999, 0.4999]};
    }
  }
endclass : my_seq_item

This would be similar to a solution found here:

https://verificationacademy.com/forums/t/constrain-a-relation-between-arrays-of-signed-values-in-systemverilog/39108

Another idea I am working on can be found in this Q&A:

https://verificationacademy.com/topics/systemverilog/verilog-basics-for-systemverilog-constrained-random-verification/

It is important that rx_data is properly constrained using the range [-0.7999, 0.4999], otherwise the verification solution is incomplete.