Hi,
I have UVM Testbench and in UVM Environment I have instantiate and create scoreboard and reference model class.
I wanted to bring the output of reference model to scoreboard in order to do the comparison with DUT output.
Is it advisable to to declare the output signals of reference model in the interface and in the scoreboard get the interface and do the compare?
Please suggest me the recommended approach.
Thanks.
In reply to Yeptho:
If your reference model is class based, there is no need to put it into a SystemVerilog interface. You can put it as a component inside the scoreboard or a component in front of the scoreboard. See Predictors | Verification Academy
In reply to dave_59:
Thank you dave.
by the way, indeed my reference model is a class based and it is extended from uvm_component.
I presume your statement “component inside the scoreboard” meaning instantiate reference model inside the scoreboard where Hierarchal wise scoreboard will be the parent for reference class?
If that is so, from the scoreboard write function, do I need to feed inputs data to reference model?