Connecting Interface ports to clocking blocks

SystemVerilog
,
1

I am having some bother with clocking blocks…

I am using this paper as a reference - see Figure 17 for my case

I have a bind statement that instantiates an interface inside the hierarchy of a module. To specify the connections i use ports on the iterface.

Inside the interface I connect the input ports to the inputs of the clocking block. See section 14.5 of the Systemverilog LRM. This will then assign values to the wires after skews have been taken into account.
My problem is that the values on the input ports are not assigned to the wires in the interface via the clocking.
Any thoughts anyone?

Thanks



interface mig_usr_if(            input logic                         CLOCK        , 
                                 input logic                         RESET        , 
                                 input addr_lt                       ADDR         , 
                                 input cmd_lt                        CMD          , 
                                 input data_lt                       WR_DATA      , 
                                 inout logic                         RDY          , 
                                 inout MIG_USR_IF_data_lt            RD_DATA      , 
                                 inout logic                         RD_DATA_END  , 
                                 inout logic                         RD_DATA_VALID);

                
                parameter                                  setup_time = 1ns             ;
                parameter                                  hold_time  = 1ns             ;

                addr_lt                                    addr                         ;
                cmd_lt                                     cmd                          ;
                data_lt                                    wr_data                      ;
                logic                                      rdy                          ;
                data_lt                                    rd_data                      ;
                logic                                      rd_data_end                  ;
                logic                                      rd_data_valid                ;
                


assign     RDY                 = rdy              ,
           RD_DATA             = rd_data          ,
           RD_DATA_END         = rd_data_end      ,
           RD_DATA_VALID       = rd_data_valid    ;

  clocking mig_usr_cb @ (posedge CLOCK);
                        default input #setup_time output #hold_time   ;
                                output rdy                            ;
                                output rd_data                        ;
                                output rd_data_end                    ;
                                output rd_data_valid                  ;
                                input  addr            = ADDR         ;
                                input  cmd             = CMD          ;
                                input  wr_data         = WR_DATA      ;
  endclocking:mig_usr_cb 

endinterface : mig_usr_if
2

Below is an example on how interfaces are typically defined.

package counter_pkg;
  timeunit 1ns; timeprecision 100ps;
  `define TOP counter_tb
  const int MAX_COUNT=6, MIN_COUNT=3; 
  typedef enum {CT_LOAD, CT_RESET, CT_WAIT, CT_DONE} ct_scen_e;
endpackage : counter_pkg
 interface counter_if (input logic clk);
     import counter_pkg::*; 
     logic[3:0] data_in;
     logic ld;
     logic[3:0] counter;
     logic rst_n;
     ct_scen_e kind_cp; // for debug only
            
            
     clocking driver_cb @ (posedge clk);
         output rst_n, data_in, ld, kind_cp; 
         input counter;
     endclocking : driver_cb
  
     clocking mon_cb @ (posedge clk);
         input rst_n, data_in, ld, kind_cp; 
         input counter;
     endclocking : mon_cb
     
     modport drvr_if_mp (clocking driver_cb);
     modport mon_if_mp (clocking mon_cb);
     
     
 endinterface : counter_if

Ben Cohen http://www.systemverilog.us/

  • SystemVerilog Assertions Handbook, 3rd Edition, 2013
  • A Pragmatic Approach to VMM Adoption
  • Using PSL/SUGAR … 2nd Edition
  • Real Chip Design and Verification
  • Cmpt Design by Example
  • VHDL books
3

In reply to ben@SystemVerilog.us:

The reason my definition is different to yours is that i am using a bind on the port connection side. The paper referenced provides clear justification for this method, hence why i have duplicated.
My question more relates to the clocking blocks in LRM section 14.5. This discusses hierarchical expressions. The port is in the same scope as the clocking block so i see no reason why this shouldn’t work? There are no 2-state variables or anything that gets in the way.

However i think that i’ll re-examine my clocking blocks… thanks for your input.