Below is an example on how interfaces are typically defined.
package counter_pkg;
timeunit 1ns; timeprecision 100ps;
`define TOP counter_tb
const int MAX_COUNT=6, MIN_COUNT=3;
typedef enum {CT_LOAD, CT_RESET, CT_WAIT, CT_DONE} ct_scen_e;
endpackage : counter_pkg
interface counter_if (input logic clk);
import counter_pkg::*;
logic[3:0] data_in;
logic ld;
logic[3:0] counter;
logic rst_n;
ct_scen_e kind_cp; // for debug only
clocking driver_cb @ (posedge clk);
output rst_n, data_in, ld, kind_cp;
input counter;
endclocking : driver_cb
clocking mon_cb @ (posedge clk);
input rst_n, data_in, ld, kind_cp;
input counter;
endclocking : mon_cb
modport drvr_if_mp (clocking driver_cb);
modport mon_if_mp (clocking mon_cb);
endinterface : counter_if
Ben Cohen http://www.systemverilog.us/
- SystemVerilog Assertions Handbook, 3rd Edition, 2013
- A Pragmatic Approach to VMM Adoption
- Using PSL/SUGAR … 2nd Edition
- Real Chip Design and Verification
- Cmpt Design by Example
- VHDL books