I am having some bother with clocking blocks…
I am using this paper as a reference - see Figure 17 for my case
I have a bind statement that instantiates an interface inside the hierarchy of a module. To specify the connections i use ports on the iterface.
Inside the interface I connect the input ports to the inputs of the clocking block. See section 14.5 of the Systemverilog LRM. This will then assign values to the wires after skews have been taken into account.
My problem is that the values on the input ports are not assigned to the wires in the interface via the clocking.
Any thoughts anyone?
Thanks
interface mig_usr_if( input logic CLOCK ,
input logic RESET ,
input addr_lt ADDR ,
input cmd_lt CMD ,
input data_lt WR_DATA ,
inout logic RDY ,
inout MIG_USR_IF_data_lt RD_DATA ,
inout logic RD_DATA_END ,
inout logic RD_DATA_VALID);
parameter setup_time = 1ns ;
parameter hold_time = 1ns ;
addr_lt addr ;
cmd_lt cmd ;
data_lt wr_data ;
logic rdy ;
data_lt rd_data ;
logic rd_data_end ;
logic rd_data_valid ;
assign RDY = rdy ,
RD_DATA = rd_data ,
RD_DATA_END = rd_data_end ,
RD_DATA_VALID = rd_data_valid ;
clocking mig_usr_cb @ (posedge CLOCK);
default input #setup_time output #hold_time ;
output rdy ;
output rd_data ;
output rd_data_end ;
output rd_data_valid ;
input addr = ADDR ;
input cmd = CMD ;
input wr_data = WR_DATA ;
endclocking:mig_usr_cb
endinterface : mig_usr_if