In reply to cgales:
I apologize for confusing you. You are rigth. Test_int module is just a stub for testing interfaces and I designed it wrong.
New module:
module test_int (
// Synchro signal and reset
input logic ACLK,
input logic ARESETN,
// Interface S_AXIS_DATA
input logic S_AXIS_DATA_TVALID,
output logic S_AXIS_DATA_TREADY,
input logic S_AXIS_DATA_TLAST,
input logic [31:0] S_AXIS_DATA_TDATA,
input logic [7:0] S_AXIS_DATA_TUSER,
// Interface M_AXIS_DATA
output logic M_AXIS_DATA_TVALID,
input logic M_AXIS_DATA_TREADY,
output logic M_AXIS_DATA_TLAST,
output logic [31:0] M_AXIS_DATA_TDATA,
output logic [7:0] M_AXIS_DATA_TUSER
);
assign M_AXIS_DATA_TDATA = S_AXIS_DATA_TDATA;
assign M_AXIS_DATA_TUSER = S_AXIS_DATA_TUSER;
assign S_AXIS_DATA_TREADY = M_AXIS_DATA_TREADY;
assign M_AXIS_DATA_TVALID = S_AXIS_DATA_TVALID;
assign M_AXIS_DATA_TLAST = S_AXIS_DATA_TLAST;
endmodule
Waveform with problem:
