In reply to Pavel:
It is not very clear on what you are trying to accomplish with this environment. I am particularly confused by the test_int() module.
When an AXI4Stream Master and Slave communicate, their signals are tied directly together so that they can handshake appropriately. Instead, in test_int(), you have the Master and Slave disconnected and it is forcing TREADY and TVALID independent of what the Master and Slave are actually signalling. This will cause improper behavior since the Master may not have TVALID asserted, yet test_int() may assert it. Or similarly, the test_int() may assert TREADY even if the Slave doesn’t have it asserted.
I recommend that you remove modify test_int() so that it simply connects the Master directly to the Slave. Also, you don’t want any ff’s in test_int() since that will introduce additional clock delays.