Conditional Statement in 'repeat loop'

SystemVerilog
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6

In reply to Shashank Gurijala:



// Code your testbench here
// or browse Examples
module transition_bins;
 bit [3:0] data;
 covergroup cg;
 c1: coverpoint data { 
 
				      bins d1[]   =  (9 => 3);
 
		         	      bins d2[]   =  (4 => 8 => 12);
 
				      bins d3[]   =  (2,3 => 4,5); 
 
	 		              bins d4[]   =  (2,3,4 => 5,6,7); 
 
				      bins d5[]   =  (4'hd[*2] => 5,6,7);
 
				      bins d6[]   =  (7[*2:4]); 
 
				      bins d7     =  (9 => 5[->3] => 11);
 
				      bins d8     =  (12 => 15[=3] => 10);
 
				      }
 
 
	endgroup: cg
 
	initial 
 
		begin
 
			cg c = new;
 
          while (c.get_inst_coverage!=100.00) //what should I change so that when the coverage is 100%, the repeat block terminates?
 
				begin
 
					data = $random;
 
					$display("\ndata = %0h",data);
 
					c.sample();
             
 
 
 
				end
 
			$display("\nCoverage = %0.4f%%",c.get_inst_coverage());
 
 
     end
 
endmodule