Hello! Here is a sample code to verify the transitional bins. I’ve repeated the loop randomly for 100000 times for functional coverage to become 100%. Now I want to add a condition in the repeat loop that at coverage = 100%, the block has to terminate. What changes should I make to the code? modu…

In reply to Shashank Gurijala : // Code your testbench here // or browse Examples module transition_bins; bit [3:0] data; covergroup cg; c1: coverpoint data { bins d1[] = (9 => 3); bins d2[] = (4 => 8 => 12); bins d3[] = (2,3 => 4,5); …

Conditional Statement in 'repeat loop'

SystemVerilog

dave_59 May 2, 2022, 8:25pm 2

In reply to Shashank Gurijala:

See the break statement.