Concatenation of instance name with loop index

SystemVerilog
,
1

Hello,

I have a for loop inside which I am trying to concatenate a string with the loop index as below,

string str;
for(i=0;i<244; i++)
begin
str = {A_inst,i};
if(str.sig == 1)
begin end
end

Where, A_inst is instance path name and “sig” is a signal name in that instance.I am getting a compilation error. Let me know where I am going wrong.

2

It is not possible within the SystemVerilog language to access an identifier using a dynamic string name. Some program created these 244 unique instance names in your source file. Or maybe it was generated manually. You will have to use a program or script to generate the code here, or create it by hand.

3

In reply to dave_59:

If the code is simple enough then you can use define to do the same job.


`define MOD(inst) mod``inst``.sig

....
for(i=0;i<244;i++) begin
 if(`MOD(i) == 1'b0) begin
 end
....
end

This code is working for me on questa & modelsim

4

In reply to Naven8:

`define MOD(inst) modinst.sig

I tried to use above defines, ie: MOD(0),MOD(1),MOD(2)… But I get warnings saying MOD is getting redefined and it takes the value of last define.

EX:
define MOD(0) module_ex_inst_``0`` define MOD(1) module_ex_inst_1
define MOD(2) module_ex_inst_``2`` define MOD(3) module_ex_inst_3
`define MOD(4) module_ex_inst_4

Let me know what is the problem.

5

In reply to Chandrashekhar Goudar:

There is no need to re-define the macro in your case. Just define the macro once and pass different values to access different sub modules. I have given proper code in my last example. Just use the same code.

6

In reply to Naven8:

Its replacing “inst” with i but not the value of i.

7

In reply to Chandrashekhar Goudar:

Please share your code.

8

In reply to Naven8:

It would really help if BOTH of you shared a small COMPLETE example of your code.

9

In reply to dave_59:

Sorry. Looks like i have understood the requirement wrongly. I didn’t see any other way other than replicating the code for each module instance.

Below is a small example which is doing the same.

module m1;
  `define D(x) mod``x``.sig
  m2#(4) mod0();
  m2#(5) mod1();
  initial begin
    #5;
    for(int j=0;j<2;j++) begin
      case(j)
        0: $display("Print in case0 %d", `D(0)); // Put a function call instead of $display if some common thing should be done.
        1: $display("Print in case1 %d", `D(1));
      endcase
    end
  end
endmodule

module m2;
  parameter m1=1;
  reg [10:0]sig;
  initial begin
    sig =m1;
  end
endmodule