Concatenation of instance name with loop index

SystemVerilog
,
3

In reply to dave_59:

If the code is simple enough then you can use define to do the same job.


`define MOD(inst) mod``inst``.sig

....
for(i=0;i<244;i++) begin
 if(`MOD(i) == 1'b0) begin
 end
....
end

This code is working for me on questa & modelsim