Compile race caused by blocking assginment

SystemVerilog
,
1

I am confused by the race conditions,and i want to get a surely answer about the blow 2 questions of 2 statement:
1.

module xxx;
xxxxx

initial begin

    wait(posdge clk);
    error <= 1;

end
always @(posdege clk) begin
    if(error)begin
        interupt <= 1;
    end
end
endmodule

question 1:“eror<=1” and “if(error)begin” there is no race conditions.is this right?

module xxx;
xxxxx

initial begin

    wait(posdge clk);
    error = 1;

end
always @(posdege clk) begin
    if(error)begin
        interupt <= 1;
    end
end
endmodule

question 2:“eror=1” and “if(error)begin” here is a race conditions.is this right?

looking forward to your answer.

2

In reply to yongci:

Please use code tags making your code easier to read. I have added them for you.

The try to show complete, runnable examples Asking better questions on the Verification Academy Forums with EDAPlayground - Verification Horizons