Below are the 2 cases . Case 1 works fine but getting error in case 2 .
Case 1 :
File Name : pkg1.sv
package pkg1;
class abc1;
int x=1;
task access();
x++;
endtask
endclass
endpackage
File Name : pkg2.sv
package pkg2;
class abc2;
abc1 abc1_h;
function new();
abc1_h = new();
$display(abc1_h.x);
endfunction
endclass
endpackage
File Name : top.sv
`timescale 1ns/1ns
`include "pkg1.sv"
import pkg1::*;
`include "pkg2.sv"
import pkg2::*;
module top;
int i=0;
abc1 abc1_h;
abc2 abc2_h;
initial begin
abc1_h = new();
abc2_h = new();
end
endmodule
Case 2 :
File Name : abc1.sv
class abc1;
int x=1;
task access();
x++;
endtask
endclass
File Name : top1.sv
`timescale 1ns/1ns
`include "abc1.sv"
`include "pkg2.sv"
import pkg2::*;
module top1;
int i=0;
abc1 abc1_h;
abc2 abc2_h;
initial begin
abc1_h = new();
abc2_h = new();
end
endmodule
So basically if I define abc1 class in package and then include and import pkg1 then everything works fine .
But I am getting below error in case 2 :
SV package not allowed to access item declared in compilation unit scope . What is compilation Unit Scope ? please explain .
Neither case should work. A package only has visibility to identifiers in the package itself, or those have been imported into it. The import pkg1::* needs to be inside the scope of pkg2 in order to see the declaration of abc1.
The compilation unit scope is an area of code that is not inside any other package/module/interface.
In reply to dave_59:
Hi dave,
According to you “case 1” should not work. But why the following code works. In following codes, tb_pkg have tb_components(env extended from uvm_env, agents extended from uvm_agent…) and uvm_pkg is not imported inside tb_pkg.
Even i simulated the “case 1” in incisive and i did not get any error, it is working fine.
file: tb_top.sv
`include "uvm_macros.svh"
import uvm_pkg::*;
`include "../tb_pkg.sv" //have TB Components extended from uvm_components
import tb_pkg::*
Module tb_top;
..
..
endmodule
In reply to rahulkumarkhokher@gmail.com:
What you have shown me is not legal syntax and may not work in other tools. A SystemVerilog package is designed to be a self-contained unit with no other dependencies except for other package imports.
Items within packages shall not have hierarchical references to identifiers
except those created within the package or made visible by import of another package. A package shall not
refer to items defined in the compilation unit scope. (
In reply to dave_59:
Ok, I will simulate the above code in other tool also.
As you said “A SystemVerilog package is designed to be a self-contained unit with no other dependencies except for other package imports”
Does this mean SV package is compiled as separate compilation unit?
In reply to rahulkumarkhokher@gmail.com:
Essentially, yes; a package is like a separate compilation unit. There are differences when it comes to compiler directives like `define macros. These are pre-processed before the compiler recognizes any scope like a package, but let’s not get into that now.
To make your code work in any simulation or synthesis tool, you need to put your import inside the package that us going to use the imported identifiers.