In reply to rahulkumarkhokher@gmail.com:
What you have shown me is not legal syntax and may not work in other tools. A SystemVerilog package is designed to be a self-contained unit with no other dependencies except for other package imports.
Items within packages shall not have hierarchical references to identifiers
except those created within the package or made visible by import of another package. A package shall not
refer to items defined in the compilation unit scope. (