Combinationally sampling an input in clocking block

SystemVerilog
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5

In reply to MayurKubavat:
You should not be using any input or output skews unless your DUT is a gate-level design with timing. Use the implicit default, or write

default input #1step output #0;

Your while loop is effectively double sampling ready. Try

cb.wren <= 0;
@(cb iff ready); // Wait until ready
cb.wren <= 1;