In reply to bitfiddler0:
Not sure how making input skew Zero for ready signal solves the problem, as clocking block will sample 0step before clock edge or 1step based on input skew. But still there no way to achieve driving of ready/wren at same point where both the signal comes from two opposite blocks, testbench and design.
For synchronous handshakes either your testbench environment should wait for ready signal(sampled in testbench on clock edge, using clocking block). In which there will be a One cycle delay between ready/wren. Or testbench drives wren independently regardless of ready signal, but needs to hold wren until ready high is sampled, which means design accepted the wren signal. This is similar to AHB protocol minus pipeline.