In reply to MayurKubavat:
In reply to bitfiddler0:
Hi,
I doubt you can overcome this situation with “One way to overcome this, is to use “input #0 ready” in the clocking block. However, I’ve been told that this is a bad idea.” this. Have you tried this?
To drive wren signal on same cycle where ready is asserted, you’ll have to bypass clocking block. And use wait construct for ready high condition. However if your spec refers to synchronous signals, you might be missing something in driving protocol. As for synchronous designs you should be able to achieve handshakes through clocking block, which is not case here.
Also, your randomized delay approach works ok, but if you want control on randomization as well, use packet based delays with constraint randomization.
Yes I have tried “input #0 ready” and it works for this particular circuit I’m testing.
Can you elaborate on what you mean by “However if your spec refers to synchronous signals, you might be missing something in driving protocol” ?
Really appreciate your help.