I want to generate a 39.6 ns period clock from my test bench. The following code generates a 40 ns clock instead. Can anyone tell me what is the problem? How to fix this precision problem? I use Modelsim simulator. `timescale 1ns/100ps localparam T = 39.600 logic clk = 1'b0 ; always #(T/2) clk …

In reply to Mitu Raj : Works for me. Please show a complete example. `timescale 1ns/100ps module top(); localparam T = 39.600; logic clk = 1'b1 ; always #(T/2) clk = ~ clk ; initial begin repeat (10) @(posedge clk) $display($realtime); $finish; end endmodule # run -all # 39.6 # 7…

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Clock precision setting

SystemVerilog

dave_59 March 5, 2021, 5:40pm 9

In reply to bachan21:

This is something you could easily answer by trying yourself.