Clock Period Configuration-UVM Help!

UVM
,
1

Hi everyone

I’m a newbie on UVM verification, I’m building a environment to verify my design. In my design It has a clock input whose the clock frequency can change from user. I intend to test the design with with different clock frequency. How can I configure this?

Please have a look at my testbench top

module wdt_top_tb;

// `include “uvm_macros.svh”
parameter cycle_1 = 15.625;
parameter cycle_2 = 20;

//Interface declaration
wdt_if vif();
wdt_clock_mux_if wdt_clk_mux_if0();

//Connects the Interface to the DUT
wt_top dut(vif.clk1,
vif.clk2,
vif.rst_b,

…)

How can I change the cycle_2 parameter with the configuration from testcase?

Thank you!

2

You didn’t show how you intended to use cycle_2 to represent the clock frequency. You can’t change the value of a parameter at run-time, but you can change the value of a variable. Fortunately, you can use the value of a variable in a procedural delay. Your clock generator can read the value from the uvm_config_db and set up the clock period.

3

In reply to dave_59:

Hi Dave

Thanks for your reply.
Here it is,
//Clock generation
always
#cycle_1 vif.clk1 = ~vif.clk1;
always
#cycle_2 vif.clk2 = ~vif.clk2;
Clk1 is fixed, clk2 varies depending on testcases.

As you said, How can I make a procedural delay? Can I write it one wdt_top_tb or open a new class for clock generator?
I’m still unclear, Can you give me an example?

Thank you!

4

In reply to Hongnhattl:

Hi Dave

I did that.

Here my code
In wdt_top module:

 initial begin
           
        $dumpfile("test1.vcd");
        $dumpvars(0,spi_top_tb);
           
        svif.SCK_PAD <= 1'b1;
        svif.MSCK <= 1'b1;
           
        start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);
        void'(uvm_config_db#(spi_config)::get(null,"uvm_test_top","config",cfg));
         begin           
                sck_cyc = cfg.sck_cyc;  
                sck_hcyc = sck_cyc/2;
                sck_hcyc_div2 = sck_hcyc/2;
           
         end  
        end
           
        //Clock generation
        always
         begin              
                #sck_hcyc_div2; 
                #sck_hcyc_div2 svif.SCK_PAD = ~svif.SCK_PAD;
         end  
        always
         begin              
                #sck_hcyc_div2 svif.MSCK = ~svif.MSCK;
                #sck_hcyc_div2; 
         end

In testlib

cfg.sck_cyc = 3.75*2;
         uvm_config_db #(spi_config)::set(this, "", "config", cfg);

Thanks and Best regards,
Nhat

5

In reply to Hongnhattl:

Hi Hongnhattl,
I tried your clock configuration concept in my one of my project,but i have following issues,

  1. I’m not able to get the cfg value inside initial begin block (used same like your below code). I tried declaring it as real/int,but the simulation hangs without clock - i’m not able to get the value from testlib. Kindly clarify.

     start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);
 void'(uvm_config_db#(spi_config)::get(null,"uvm_test_top","config",cfg));
  begin           
         sck_cyc = cfg.sck_cyc;  
         sck_hcyc = sck_cyc/2;
         sck_hcyc_div2 = sck_hcyc/2;
   end

2.In testlib, where should i use below code? In build_phase or in run_phase?.

    cfg.sck_cyc = 3.75*2;
     uvm_config_db #(spi_config)::set(this, "", "config", cfg);
  1. Can i change clock dynamically using this implementation in run_phase of testcase - Means change of configuration during testcase running.

Expecting your reply at the earliest.

Thanks & Regards
Gowri Shankar

6

In reply to tanyaa:

for #1,

i tired declaring cfg as

config cfg;

In this case, NULL Pointer dereference is the error for cfg.

begin
sck_cyc = cfg.sck_cyc;
end