Clock Period Configuration-UVM Help!

UVM
,
4

In reply to Hongnhattl:

Hi Dave

I did that.

Here my code
In wdt_top module:

 initial begin
           
        $dumpfile("test1.vcd");
        $dumpvars(0,spi_top_tb);
           
        svif.SCK_PAD <= 1'b1;
        svif.MSCK <= 1'b1;
           
        start_of_simulation_ph.wait_for_state(UVM_PHASE_STARTED);
        void'(uvm_config_db#(spi_config)::get(null,"uvm_test_top","config",cfg));
         begin           
                sck_cyc = cfg.sck_cyc;  
                sck_hcyc = sck_cyc/2;
                sck_hcyc_div2 = sck_hcyc/2;
           
         end  
        end
           
        //Clock generation
        always
         begin              
                #sck_hcyc_div2; 
                #sck_hcyc_div2 svif.SCK_PAD = ~svif.SCK_PAD;
         end  
        always
         begin              
                #sck_hcyc_div2 svif.MSCK = ~svif.MSCK;
                #sck_hcyc_div2; 
         end

In testlib

cfg.sck_cyc = 3.75*2;
         uvm_config_db #(spi_config)::set(this, "", "config", cfg);

Thanks and Best regards,
Nhat