In reply to ben@SystemVerilog.us:
1800 says that The expression on the left-hand side of the inside operator is any singular expression.
It looks like the inside does not work on real or realtime types.
The use of comparison operators is thus best suited.
property p_clk_freq2;
realtime current_time;
@ (posedge clk)
disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=> (1, $display ("p=%t", $realtime - current_time))
##0 ($realtime - current_time) <= clk_period + 1ns and // sequence and
($realtime - current_time) >= clk_period - 1ns;
endproperty
ap_clk_freq2: assert property (p_clk_freq2);
// ALSO OK
property p_clk_freq3;
realtime current_time;
@ (posedge clk)
disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=> (1, $display ("p=%t", $realtime - current_time))
##0 (($realtime - current_time) <= clk_period + 1ns && // logical and
($realtime - current_time) >= clk_period - 1ns);
endproperty
ap_clk_freq3: assert property (p_clk_freq3);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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