In reply to leya:
OK, the following works, I had 26 passes and 3 failures.
property p_clk_freq2;
realtime current_time;
@ (posedge clk)
// disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=> (1, $display ("p=%t", $realtime - current_time))
// (clk_period <= ($realtime - (current_time-0.001ns))||
// ($realtime - (current_time+0.001ns)));
// 11.4.13 Set membership operator
// inside_expression ::= expression inside { open_range_list }
//int a, b, c;
// if ( a inside {b, c} ) ...
##0 ($realtime - current_time) <= clk_period + 1ns and
($realtime - current_time) >= clk_period - 1ns;
endproperty
ap_clk_freq2: assert property (p_clk_freq2);
I have to analyze why the solution with the inside fails.
Below is my Testbench code.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, clk2, a, b;
realtime clk_period= 20ns;
default clocking @(posedge clk); endclocking
initial forever #(clk_period/2 + a*1ns -b*1ns) clk=!clk;
initial forever #10ns clk2=!clk2;
initial begin
$timeformat(-9, 1, "ns", 8);
$display("%t", $realtime);
end
property p_clk_freq;
realtime current_time;
@ (posedge clk)
// disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=>
// (clk_period <= ($realtime - (current_time-0.001ns))||
// ($realtime - (current_time+0.001ns)));
// 11.4.13 Set membership operator
// inside_expression ::= expression inside { open_range_list }
//int a, b, c;
// if ( a inside {b, c} ) ...
($realtime - current_time) inside {clk_period - 0.2ns, clk_period + 0.2ns}
endproperty
ap_clk_freq: assert property (p_clk_freq);
property p_clk_freq2;
realtime current_time;
@ (posedge clk)
// disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=> (1, $display ("p=%t", $realtime - current_time))
// (clk_period <= ($realtime - (current_time-0.001ns))||
// ($realtime - (current_time+0.001ns)));
// 11.4.13 Set membership operator
// inside_expression ::= expression inside { open_range_list }
//int a, b, c;
// if ( a inside {b, c} ) ...
##0 ($realtime - current_time) <= clk_period + 1ns and
($realtime - current_time) >= clk_period - 1ns;
endproperty
ap_clk_freq2: assert property (p_clk_freq2);
initial begin
bit va, vb;
repeat(200) begin
@(posedge clk);
if (!randomize(va, vb) with
{ va dist {1'b1:=1, 1'b0:=3};
vb dist {1'b1:=1, 1'b0:=3};
}) `uvm_error("MYERR", "This is a randomize error")
a <= va;
b <= vb;
end
$stop;
end
endmodule
Ben Cohen
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