In reply to ben@SystemVerilog.us:
Hi Ben,
Thank you for the input.
I have tried to change the value of clock_input.
Still the assertion is passing.
Can you suggest any changes?
property p_clk_freq;
realtime current_time;
@ (posedge clk)
disable iff ( !(!(reset) && (flag)))
('1, current_time = $realtime) |=>
(clock_input <= ($realtime - (current_time-0.001ns))|| ($time - (current_time+0.001ns)));
endproperty
ap_clk_freq: assert property (clk_freq);
Thanks,
Leya