In reply to ben@SystemVerilog.us:
To test your code, you may want to use a modified approach similar to the shown below where I introduce random jitter in the clock. This is a quick way to verify your assertion.
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk=1, a;
bit[0:1] t;
default clocking @(posedge clk); endclocking
initial forever begin
#298 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns clk=!clk;
end
else #2ns clk=!clk;
#398 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns;
end
else #2ns;
#300 clk=!clk;
end
property p_clk_hi;
realtime v;
@(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
realtime v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf